The present invention relates generally to digital circuits, and more particularly, to a synchronous clock multiplexer.
Integrated circuits include circuit modules that perform various tasks and operate in tandem. Examples of circuit modules include processors, logic gates, flip-flops, latches, system buses, and so forth. These circuit modules are driven by clock signals. Depending on the system requirements, different circuit modules may require different clock signals (of different phases and frequencies) for their operation; e.g., an integrated circuit may include one set of modules that operates in a first clock domain and another set of modules that operates in a second clock domain. Such integrated circuits are referred to as asynchronous integrated circuits.
A clock multiplexer is used to provide clock signals from different clock sources to the circuit modules. FIG. 1 is a schematic block diagram of a synchronous clock multiplexer 100. The synchronous clock multiplexer 100 has two input terminals for receiving first and second clock input signals CLK0 and CLK1, a select terminal for receiving a select signal SELECT and an output terminal for providing either of the first and second clock signals CLK0 and CLK1 as an output clock signal OUT CLOCK. The synchronous clock multiplexer 100 provides the first clock input signal CLK0 as the output clock signal OUT CLOCK signal when the select signal SELECT is low and provides the second input clock signal CLK1 as the output clock signal OUT CLOCK when the select signal SELECT is high. The synchronous clock multiplexer 100 synchronously provides one of the first and second clock input signals when the select signal SELECT transitions from low to high state, or vice-versa.
However, on certain occasions, when the select signal SELECT transitions from high to low, the first clock input signal CLK0 may not be available at the input terminal, or when select signal SELECT transitions from low to high, the second clock input signal CLK1 may not be available at the input terminal due to, for example, an error in corresponding clock sources. In such cases, the synchronous clock multiplexer 100 generates an undesired clock signal or does not generate the clock signal, leading to erroneous operation of the circuit modules and the integrated circuit.
Therefore, it would be advantageous to have a synchronous clock multiplexer circuit that detects the presence of clock input signals at its input terminals when the select signal is transitioning, generates an output clock signal based on the presence of a clock input signal, and does not generate an erroneous output when a selected clock signal is not available.